Array substrate, display panel and display device

ABSTRACT

An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of gate lines and a plurality of data lines. The plurality of gate lines and the plurality of data lines define rows of sub-pixel regions, each of the sub-pixel regions includes two thin film transistors and a pixel electrode, and the two thin film transistors are both connected with the pixel electrode. Gate electrodes of two thin film transistors in an (n)th row of sub-pixel regions of the rows of sub-pixel regions are respectively connected with an (n)th gate line and an (N+1)th gate line of the plurality of gate lines, K≥n≥1, n and K are integers, and K is an amount of rows of the sub-pixel regions.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the National Stage of PCT/CN2019/071809 filed onJan. 15, 2019, which claims priority under 35 U.S.C. § 119 of ChineseApplication No. 201810549269.3 filed on May 31, 2018, the disclosure ofwhich is incorporated by reference.

TECHNICAL FIELD

Embodiments of the disclosure relate to an array substrate, a displaypanel and a display device.

BACKGROUND

With the development of display technology, the resolution of a displayscreen is continuously increasing, and special display technologies suchas 3D display technology and touch display technology are alsocontinuously applied to display products. All of these developmenttrends require that the display screen can accurately write data signalsin a shorter time.

For a liquid crystal display, the conductivity of a Thin Film Transistor(TFT) is usually improved by changing a material of an active layer, soas to realize fast writing of data signals. However, when the materialof the active layer is changed, the manufacturing process of the activelayer needs to be adjusted accordingly, which results in that themanufacturing process is not mature enough for a period of time,resulting in low product yield.

SUMMARY

The embodiments of the present disclosure provide an array substrate, adisplay panel, and a display device. At least one embodiment of thepresent disclosure provides an array substrate. The array substrateincludes a plurality of gate lines and a plurality of data lines, theplurality of gate lines and the plurality of data lines define rows ofsub-pixel regions; each of the sub-pixel regions are provided with twothin film transistors; and the two thin film transistors are bothconnected with a pixel electrode of a sub-pixel region where the twothin film transistors are located. Gate electrodes of two thin filmtransistors in a sub-pixel region in an (n)th row of the rows ofsub-pixel regions are respectively connected with an (n)th gate line andan (n+1)th gate line of the plurality of gate lines, K≥n≥1, n and K areintegers, and K is an amount of rows of the sub-pixel regions.

In one example of the embodiments of the present disclosure, the twothin film transistors are respectively located on a first side and asecond side of the sub-pixel region where the two thin film transistorsare located, the first side and the second side are oppositely disposed,and the first side and the second side are sides of the sub-pixel regionwhere the two thin film transistors are located near the gate lines.

In another example of the embodiments of the present disclosure, thinfilm transistors connected with an (m)th gate line of the plurality ofgate lines are symmetrically arranged on both sides of the (m)th gateline, K≥m≥2, and m is an integer.

In another example of the embodiments of the present disclosure, the twothin film transistors each includes an active layer, and a sourceelectrode and a drain electrode which are both arranged on the activelayer, and two thin film transistors symmetrically arranged on bothsides of a same gate line share one source electrode.

In another example of the embodiments of the present disclosure, a partof a data line connected with each of the two thin film transistors isreused as a source electrode of the each of the two thin filmtransistors.

In another example of the embodiments of the present disclosure, anamount of sub-pixel regions in each row of the rows of sub-pixel regionsis equal, sub-pixel regions in adjacent rows are staggered with respectto each other, thin film transistors in an (a)th sub-pixel region ofeach row of the rows of sub-pixel regions are both connected with a samedata line, L≥a≥1, a and L are integers, and L is an amount of sub-pixelregions in each row of the rows of sub-pixel regions.

In another example of the embodiments of the present disclosure, theplurality of data lines each has a rectangular wave shape.

In another example of the embodiments of the present disclosure, therows of sub-pixel regions includes three types of sub-pixel regions thatare of red, green and blue, respectively, any two adjacent sub-pixelregions are sub-pixel regions of different types, and the two adjacentsub-pixel regions are two sub-pixel regions of a same row or differentrows.

In another example of the embodiments of the present disclosure, thearray substrate further includes a drive module, the drive moduleincludes K+2 gate drive units arranged in cascade, a first gate driveunit of the K+2 gate drive units is connected with a first gate line ofthe plurality of gate lines, a last gate drive unit of the K+2 gatedrive units is connected with a last gate line of the plurality of gatelines, a (s)th gate drive unit of the K+2 gate drive units issimultaneously connected with a (s−1)th gate line and a (s)th gate lineof the plurality of gate lines, and K+1≥s≥2.

In another example of the embodiments of the present disclosure, thedrive module further includes A gate drive units, the A gate drive unitsare not connected with any one of the plurality of gate lines, and A isa positive integer. A (A+1)th gate drive unit is connected with thefirst gate line, (A+2)th to (K+1+A)th gate drive units are respectivelyconnected with two gate lines of the plurality of gate lines, and a(K+2+A)th gate drive unit is connected with the last gate line.

In another example of the embodiments of the present disclosure, thegate drive unit includes a charging sub-unit, a buffer sub-unit, apull-up sub-unit, a holding sub-unit, and a discharging sub-unit. Thebuffer sub-unit is configured to receive an input voltage signal andcharge the charging sub-unit by using the input voltage signal; thepull-up sub-unit includes two output terminals, and the pull-up sub-unitis configured to pull up a voltage of the charging sub-unit undercontrol of a timing signal and output a gate high level through the twooutput terminals in a working stage; the holding sub-unit is configuredto control the two output terminals of the pull-up sub-unit tocontinuously output a low level during other stages other than theworking stage; the discharging sub-unit is configured to control thecharging sub-unit to discharge after end of the working stage.

In another example of the embodiments of the present disclosure, thecharging sub-unit includes a capacitor C; the buffer sub-unit includes afirst transistor T1, a source electrode of the first transistor T1 isconnected with an input voltage signal IN, a gate electrode of the firsttransistor T1 is connected with the source electrode of the firsttransistor T1, and a drain electrode of the first transistor T1 isconnected with a first terminal of the capacitor C; the pull-up sub-unitincludes a second transistor T2 and a third transistor T3, a sourceelectrode of the second transistor T2 is connected with a clock signalCLK and a source electrode of the third transistor T3, a gate electrodeof the second transistor T2 and a gate electrode of the third transistorT3 are both connected with the first terminal of the capacitor C, adrain electrode of the second transistor T2 is connected with a secondterminal of the capacitor C and a first output terminal, and a drainelectrode of the third transistor T3 is connected with a second outputterminal; the holding sub-unit includes a fourth transistor T4, a fifthtransistor T5, and a sixth transistor T6, a source electrode of thefourth transistor T4 is connected with a continuous high-level signalGCH, a gate electrode of the fourth transistor T4 is connected with thesource electrode of the fourth transistor T4, a drain electrode of thefourth transistor T4 is connected with a source electrode of the fifthtransistor T5 and a gate electrode of the sixth transistor T6, a gateelectrode of the fifth transistor T5 is connected with the firstterminal of the capacitor C, a drain electrode of the fifth transistorT5 is connected with a continuous low-level signal VGL, a sourceelectrode of the sixth transistor T6 is connected with the secondterminal of the capacitor C, and a drain electrode of the sixthtransistor T6 is connected with the continuous low-level signal VGL. Thedischarging sub-unit includes a seventh transistor T7 and an eighthtransistor T8, a source electrode of the seventh transistor T7 isconnected with a reset signal, a gate electrode of the seventhtransistor T7 is connected with the drain electrode of the fourthtransistor T4, a drain electrode of the seventh transistor T7 isconnected with a gate electrode of the eighth transistor T8, a sourceelectrode of the eighth transistor T8 is connected with the drainelectrode of the first transistor T1, and a drain electrode of theeighth transistor T8 is connected with a continuous low-level signalVSS.

In another example of the embodiments of the present disclosure, thedrive module further includes a data drive unit, the data drive unit isconfigured to input data signals to the plurality of data lines in acolumn inversion mode, and sub-pixel units connected with a same dataline are a column of sub-pixel units.

At least one embodiment of the present disclosure further provides adisplay panel including the array substrate.

At least one embodiment of the present disclosure further provides adisplay device including the display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the present disclosure will be described in moredetail below with reference to the accompanying drawings in order toenable those of ordinary skill in the art to more clearly understand theembodiments of the present disclosure.

FIG. 1 is a schematic structural diagram of an array substrate providedby at least one embodiment of the present disclosure;

FIG. 2A and FIG. 2B are enlarged views of a partial structure of anarray substrate provided by at least one embodiment of the presentdisclosure;

FIG. 3 is a schematic structural diagram of a gate drive unit providedby at least one embodiment of the present disclosure; and

FIG. 4 is a signal timing diagram provided by at least one embodiment ofthe present disclosure.

FIG. 5 is a diagram of a drive module provided bv at least oneembodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of theembodiments of the disclosure apparent, the technical solutions of theembodiment will be described in a clearly and fully understandable wayin connection with the drawings related to the embodiments of thedisclosure. It is apparent that the described embodiments are just apart but not all of the embodiments of the disclosure. Based on thedescribed embodiments herein, those skilled in the art can obtain otherembodiment, without any creative work, which shall be within the scopeof the disclosure.

Unless otherwise defined, all the technical and scientific terms usedherein have the same meanings as commonly understood by one of ordinaryskill in the art to which the present disclosure belongs. The terms,such as “first,” “second,” or the like, which are used in thedescription and the claims of the present disclosure, are not intendedto indicate any sequence, amount or importance, but for distinguishingvarious components. The terms, such as “comprise/comprising,”“include/including,” or the like are intended to specify that theelements or the objects stated before these terms encompass the elementsor the objects and equivalents thereof listed after these terms, but notpreclude other elements or objects. The terms, such as“connect/connecting/connected,” “couple/coupling/coupled” or the like,are not limited to a physical connection or mechanical connection, butmay include an electrical connection/coupling, directly or indirectly.The terms, “on,” “under,” “left,” “right,” or the like are only used toindicate relative position relationship, and when the position of theobject which is described is changed, the relative position relationshipmay be changed accordingly.

FIG. 1 is a schematic structural diagram of an array substrate providedby at least one embodiment of the present disclosure, referring to FIG.1, the array substrate includes a plurality of gate lines, commonlyreferred to as gate lines 101, and a plurality of data lines, commonlyreferred to as data lines 102. The gate lines 101 and the data lines 102define rows of sub-pixel regions 103, and two TFTs 104 are provided ineach of the sub-pixel regions 103. FIG. 2A and FIG. 2B are enlargedviews of a partial (single sub-pixel region and two sub-pixel regions)structure of the array substrate provided by the embodiment of thepresent disclosure, referring to FIG. 2B, the two TFTs 104 are bothconnected with a pixel electrode 105 of a sub-pixel region 103 where thetwo TFT are located.

Referring to FIG. 1, gate electrodes of two TFTs 104 in a sub-pixelregion in an (n)th row of the rows of sub-pixel regions 103 arerespectively connected with an (n)th gate line 101 and an (n+1)th gateline 101 of the plurality of gate lines 101, K≥n≥1, n and K areintegers, and K is an amount of rows of the sub-pixel regions 103. Forexample, as shown in FIG. 1, gate electrodes of two TFTs 104 in a firstrow of sub-pixel regions 103 of the rows of sub-pixel regions arerespectively connected with a first gate line 1011 and a second gateline 1012 of the plurality of gate lines 101. Gate electrodes of twoTFTs 104 in a second row of sub-pixel regions 103 of the rows ofsub-pixel regions are respectively connected with the second gate line1012 and a third gate line 1013 of the plurality of gate lines 101. Gateelectrodes of two TFTs 104 in a third row of sub-pixel regions 103 ofthe rows of sub-pixel regions are respectively connected with the thirdgate line 1013 and a fourth gate line 1014 of the plurality of gatelines 101, and so on.

Although only three rows of sub-pixel regions are shown in FIG. 1, it iseasy to think that the embodiment of the present disclosure may havemore or less than three rows of sub-pixel regions, and is not limited tothe example as shown in FIG. 1.

According to the embodiments of the present disclosure, two thin filmtransistors are arranged in each sub-pixel region to charge a pixelelectrode in corresponding sub-pixel region, and one gate line (exceptthe first one and the last one) is simultaneously connected with thinfilm transistors in two adjacent rows of sub-pixel regions. When acertain gate line is loaded with a voltage, thin film transistors in tworows of sub-pixel regions adjacent to the gate line are simultaneouslyturned on, at this time, a previous row of sub-pixel regions of the tworows of sub-pixel regions can be charged through a data line, and a nextrow of sub-pixel regions of the two rows of sub-pixel regions can bepre-charged at the same time. In this way, the time required forcharging the next row of subpixel regions becomes shorter, so that thisdesign can shorten the charging time of other rows of subpixel regionsexcept the first row and the last row of subpixel regions, and canrealize accurate writing of pixel voltages in a shorter time.

In addition, the above scheme does not affect the display effect. Forexample, for a full high definition (FHD) resolution (1920*1080)product, an opening time of each row of gate electrodes is about 8.6 ns,and the opening time is very short, so that the human eyes cannotrecognize the change of pixel luminance during a pre-charging stage.Therefore, the pre-charging technique has no effect on the actualdisplay.

Referring to FIG. 2B, in one example of the embodiment of the presentdisclosure, the two TFTs 104 are respectively located on a first side131 and a second side 132 of the sub-pixel region 103 where the two TFTsare located, the first side 131 and the second side 132 are oppositelydisposed, the first side 131 and the second side 132 are sides of thesub-pixel region 103 where the two TFTs are located near the gate lines.The two TFTs of one sub-pixel region are arranged on sides close toadjacent gate lines, the two sides of the two arranged TFTs areoppositely arranged, the two TFTs are respectively close to gate lineson both sides of the sub-pixel region where the two TFTs are located,and the two TFTs in each sub-pixel region are arranged on a upper sideand a lower side of the sub-pixel region, so that a second to apenultimate gate lines can be directly connected with the TFTs in thetwo adjacent rows of sub-pixel regions, and the wiring design can befacilitated. In addition, setting the TFTs on the sides of the sub-pixelregion can occupy the area of the sub-pixel region as little aspossible, thus ensuring the aperture ratio, and a larger aperture ratiocan enable more light emitted by a backlight source to pass through adisplay panel, thus achieving the effects of reducing the luminance ofthe backlight source and reducing the power consumption.

In other examples of the embodiment of the present disclosure, the twoTFTs 104 can further be arranged by other ways, for example, the twoTFTs are respectively located on the left and right sides of thesub-pixel region 103.

In the embodiment of the present disclosure, TFTs 104 connected with an(m)th gate line 101 of the plurality of gate lines 101 are symmetricallyarranged on both sides of the (m)th gate line 101, K≥m≥2, and m is aninteger. The TFTs in two rows are symmetrically arranged to furtherfacilitate the gate line to be connected with the TFTs in the twoadjacent rows of sub-pixel regions and facilitate the wiring design.

As shown in FIG. 1, the array substrate provided by the embodiment ofthe present disclosure includes K rows of sub-pixel regions, andcorrespondingly, K+1 gate lines are arranged. Except the first gate lineand the (K+1)th gate line, TFTs connected with other gate lines arearranged on both sides of the other gate lines, and TFTs connected withthe gate lines are symmetrically arranged.

In the embodiment of the present disclosure, the TFT 104 may be either abottom-gate type TFT or a top-gate type TFT.

Taking a bottom-gate type TFT as an example, and referring to FIG. 2A toFIG. 2B, the TFT 104 includes a gate electrode 110 on a substrate, agate insulating layer, an active layer 106, and a source electrode 108and a drain electrode 107 on the active layer 106. The gate electrode110 is connected with a gate line 101. As shown in FIG. 2A to FIG. 2B,the active layer 106 is connected with a pixel electrode 105 through thedrain electrode 107, and two TFTs 104 symmetrically arranged on bothsides of a same gate line 101 share one source electrode 108. The twoTFTs symmetrically arranged on both sides of the same gate line sharethe same source electrode, so that the area occupied by the sourceelectrode can be reduced, the distance between the source electrode andthe drain electrode can be increased, and the width-to-length ratio(W/L) of the TFT can be further increased. By increasing the W/L of theTFT, the working current of the TFT can be increased, and the powerconsumption can be reduced.

In the embodiment of the present disclosure, a part of a data line 102connected with each of the two TFTs 104 is reused as a source electrode108 of the each of the two TFTs, that is, the source electrode 108 is apart of the data line 102 connected with the two TFTs 104. Because thedata line is of a linear structure, in a conventional design, it isnecessary to design a block electrode to connect with the data line, andthe block electrode is the source electrode. In the present disclosure,the part of the data line is directly used as the source electrode, andthe block electrode is not designed separately, thus realizing themultiplexing of the data line. By multiplexing the data line as thesource electrode, there is no need to connect another block electrode onthe basis of the data line, thus further reducing the occupied area ofthe source electrode, and the part area can be used to increase thechannel width of the TFT, thus increasing the W/L of the TFT.

Because the TFT works in a non-saturated region most of the time when itis turned on, a calculation formula of a corresponding working currentis:I _(ds)=½u _(n) C _(ox)(W/L)[(V _(gs) −V _(th))V _(ds) −V _(ds) ²]

Therefore, in a case where the W/L of the TFT increases, the workingcurrent I_(ds) of the TFT can be increased. In the above formula, u_(n)is carrier mobility, C_(ox) is a capacitance of per unit area of thegate insulating layer, V_(gs) is a voltage between the gate electrodeand the source electrode, V_(th) is a threshold voltage of the TFT, andV_(ds) is a voltage between the source electrode and the drainelectrode.

In addition, by adopting the above-described pixel design, the TFToccupies a small area of the sub-pixel region and the aperture ratio ofthe display panel is increased, so that more light of the backlightsource can pass through the display panel, thereby reducing theluminance of the backlight source and reducing the power consumption ofthe display panel.

In the embodiment of the present disclosure, an amount of sub-pixelregions 103 in each row of the rows of sub-pixel regions 103 is equal,the sub-pixel regions 103 in adjacent rows are arranged in a staggeredmanner, TFTs 104 in an (a)th sub-pixel region 103 of each row of therows of sub-pixel regions 103 are both connected with a same data line102, L≥a≥1, a and L are integers, and L is an amount of sub-pixelregions 103 in each row of the rows of sub-pixel regions 103. Forexample, in a direction from left to right, TFTs 104 in a firstsub-pixel region in each row of the rows of sub-pixel regions 103 isconnected with a same data line 102, TFTs 104 in a second sub-pixelregion in each row of the rows of sub-pixel regions 103 is connectedwith a same data line 102, and so on.

Although it is shown in FIG. 1 that a row of sub-pixel regions includes6 sub-pixel regions, it is easy to think that the embodiments of thepresent disclosure are not limited thereto, and may include more than 6or less than 6 sub-pixel regions, for example.

Referring to FIG. 1, a staggered arrangement refers to a row alignmentarrangement in which adjacent rows of sub-pixel regions are indented andspaced apart. For example, as shown in FIG. 1, a first row and a thirdrow are arranged in alignment, and a second line has an indent relativeto the first line and the third line.

For example, in a case where there are rows of sub-pixel regions, thefirst row is aligned with rows 3, 5, 7, 9, etc., while the second row isaligned with rows 4, 6, 8, 10, etc. and has an indentation.

In the present disclosure, the TFTs are arranged at the upper side andthe lower side, and the data line is adopted to multiplex the sourceelectrode of the TFT. According to the arrangement of the sub-pixelregions, a length of the data line in the horizontal direction betweentwo rows is smaller than a width of each of the sub-pixel regions, whichis shorter than that in a case where the sub-pixel regions are arrangedin an array, thus facilitating the design of the data line. In addition,the arrangement of the sub-pixel regions can be combined with a designof subsequent red (R), green (G) and blue (B) sub-pixel regions, anddifferent pixel combination modes can be realized, thereby enhancing thedisplay effect.

For example, the embodiments of the present disclosure are not limitedto including red, green, and blue sub-pixel regions, and can furtherinclude sub-pixel regions of other colors.

In order to facilitate setting and obtain better display effect, theindent between two adjacent rows of sub-pixel regions is half the widthof one sub-pixel region, that is, the center of the sub-pixel region ofthe second row of sub-pixel regions in the two adjacent rows ofsub-pixel regions corresponds to the junction of two sub-pixel regionsof the first row of sub-pixel regions.

As shown in FIG. 1, the data line 102 has a rectangular wave shape.Because the sub-pixel regions of adjacent rows are arranged in astaggered manner, the TFTs in the (a)th sub-pixel region of each row ofsub-pixel regions can be connected by a data line with a rectangularwavy shape.

For example, in order to facilitate the connection of the data line 102and the TFT 104, the TFT 104 is disposed at a corner of the sub-pixelregion, as shown in FIG. 1, the TFTs 104 in the first row of sub-pixelregions are disposed at a upper right corner and a lower right corner ofthe sub-pixel region, and the TFTs 104 in the second row of sub-pixelregions are disposed at a upper left corner and a lower left corner ofthe sub-pixel region. FIG. 1 is only an example, in other examples,other arrangements can also be adopted, for example, TFTs 104 in eachrow of sub-pixel regions in FIG. 1 can be arranged in a upper leftcorner and a lower left corner of the sub-pixel region, in this case,the data lines in FIG. 1 can be designed in a shape that is horizontallyreversed along a left side of the sub-pixel regions corresponding to thesecond row, however, it is worth noting that TFTs connected with eachgate line are no longer symmetrically arranged in this arrangement.

In the embodiments of the present disclosure, three types of sub-pixelregions 103 of red, green and blue are arranged on the array substrate,and any two adjacent sub-pixel regions 103 are sub-pixel regions 103 ofdifferent types, and the two adjacent sub-pixel regions are twosub-pixel regions of a same row or different rows. As shown in FIG. 1,any two adjacent sub-pixel regions 103 in a same row are different typesof sub-pixel regions 103, any two adjacent sub-pixel regions 103 indifferent rows are also different types of sub-pixel regions 103, andthe sub-pixel regions 103 with different shadows in FIG. 1 representdifferent types of sub-pixel regions 103. According to this arrangement,the three sub-pixels forming a triangular position (convex shape) in thetwo adjacent rows are respectively R, G and B sub-pixel region, thusforming a pixel region. Compared with a pixel region formed by threesub-pixels in a same row, the luminous shape is smoother, the graininessis smaller, and the display effect is better. For example, in FIG. 1,the first and second sub-pixel regions of the first row and the firstsub-pixel region of the second row are respectively R, G and B sub-pixelregions to form one pixel region, or the second sub-pixel region of thefirst row and the first and second sub-pixel regions of the second rowin FIG. 1 are respectively R, G and B sub-pixel regions to form onepixel region.

In adopting the above RGB sub-pixel regions, the combination ofsub-pixel regions can also be in other ways, for example, threesub-pixels side by side in one row form a pixel region. Therefore, thedisplay device made of the array substrate can cooperate with differentdisplay algorithms to realize different pixel combinations and enrichthe display effect.

In the embodiments of the present disclosure, the array substratefurther includes a drive module, and the drive module includes aplurality of gate drive units arranged in cascade. The plurality of gatedrive units arranged in cascade, that is, adopting a gate drive mode ofa Gate On Array (GOA), and the plurality of gate drive units arearranged on a base substrate of the array substrate. Optionally, thedrive module further includes a data drive unit, for example, the datadrive unit can be disposed on the base substrate of the array substrateor can not be disposed on the base substrate of the array substrate.

The plurality of gate drive units, which are arranged in cascade, areused for controlling gate lines connected with the plurality of gatedrive units to be sequentially loaded with a high voltage. The datadrive unit is used for controlling a data line to input display datawhen the gate line is loaded with the high voltage. Signal driving isperformed by the gate drive unit and the data drive unit, so that thedisplay device can normally work.

In the embodiments of the present disclosure, the drive module includesK+2 gate drive units arranged in cascade, a first gate drive unit and alast gate drive unit of the K+2 gate drive units are connected with agate line, the first gate drive unit of the K+2 gate drive units isconnected with a first gate line, the last gate drive unit of the K+2gate drive units is connected with a last gate line, and a (s)th gatedrive unit of the K+2 gate drive units are simultaneously connected witha (s−1)th and a (s)th gate lines, and K+1 In this way, one gate driveunit is connected with two gate lines (that is, an output of one gatedrive unit can be used as an input of two gate lines simultaneously),TFTs in three rows of sub-pixel units can be powered up simultaneously,data signals provided by data lines can be written into pixel electrodesthrough TFTs in the three rows of sub-pixel units, and charging,pre-charging and charge neutralizing are respectively carried out forthe three rows of sub-pixel units, thus saving charging time.

An amount of the gate lines on the array substrate is K+1, K+2 gatedrive units are designed, a first gate drive unit is connected with thefirst gate line, a second gate drive unit is connected with the firstgate line and a second gate line, a third gate drive unit is connectedwith the second gate line and a third gate line, and so on.

Optionally, the drive module further includes A gate drive units, the Agate drive units are not connected with any one of the gate lines, and Ais a positive integer. A (A+1)th gate drive unit is connected with thefirst gate line, (A+2)th to (K+1+A)th gate drive units are respectivelyconnected with two gate lines, and a (K+2+A)th gate drive unit isconnected with the last gate line. The A grid drive units are arrangedin front of a display region and are not connected with any one of thegate lines, so that the unstable starting of the gate drive unit and theinfluence on the normal operation of the display device are avoided. TheA gate drive units and the K+2 gate drive units are also arranged incascade, and the A gate drive units are positioned before the K+2 gatedrive units.

The operation process of the drive module will be described below withsome examples.

When the drive module works, each of the gate drive units outputs adrive signal to two gate lines simultaneously. When an (A+1)th gatedrive unit works, the first gate line connected with the (A+1)th gatedrive unit loads a high level of a gate electrode, one row of TFTs inthe first row of sub-pixel units are turned on, and at this time,electric signals are written through the data lines to neutralize theelectric quantity of the first row of sub-pixel units. When an (A+2)thgate drive unit works, the first and second gate lines connected withthe (A+2)th gate drive unit are loaded with the high level of the gateelectrode, and two rows of TFTs in the first row of sub-pixel units andone row of TFTs in the second row of sub-pixel units are turned on. Atthis time, electric signals are written through data lines to pre-chargethe first row of sub-pixel units and neutralize the electric quantity ofthe second row of sub-pixel units. When an (A+3)th gate drive unitworks, the second and third gate lines connected with the (A+3)th gatedrive unit are loaded with the high level of the gate electrode, anotherrow of TFTs in the first row of sub-pixel units, two rows of TFTs in thesecond row of sub-pixel units, and one row of TFTs in the third row ofsub-pixel units are turned on, at this time, electric signals arewritten through data lines to charge the first row of sub-pixel units,pre-charge the second row of sub-pixel units, and neutralize theelectric quantity of the third row of sub-pixel units, and so on. Inthis design, because each of the gate drive units is connected with twogate lines, each row of sub-pixel units can be charged when threeconsecutive gate drive units work, thus shortening a working time ofeach of the gate drive units, that is, prolonging a charging time ofeach row of sub-pixel unis. Because voltage polarities of the pixelelectrodes of two adjacent frames of images are opposite, the voltageleft in the previous frame can be neutralized by electric quantityneutralization, and then performing a pre-charge to make the voltageclose to a target voltage, and finally performing a charge to make thevoltage reach the target voltage.

FIG. 3 is a schematic structural diagram of a gate drive unit providedby at least one embodiment of the present disclosure, referring to FIG.3, the gate drive unit includes a charging sub-unit 201, a buffersub-unit 202, a pull-up sub-unit 203, a holding sub-unit 204, and adischarging sub-unit 205.

The buffer sub-unit 202 is configured to receive an input voltage signaland charge the charging sub-unit 201 by using the input voltage signalIN. The pull-up sub-unit 203 includes two output terminals (a firstoutput terminal OUTPUT(n) and a second output terminal OUTPUT(n+1)), andthe pull-up sub-unit 203 is used to pull up a voltage of the chargingsub-unit under control of a timing signal and output a gate high levelthrough the two output terminals in a working stage. The holdingsub-unit 204 is configured to control the two output terminals of thepull-up sub-unit to continuously output a low level during other stagesother than the working stage. The discharging sub-unit 205 is configuredto control the charging sub-unit to discharge after end of the workingstage. By designing the structure of the gate drive unit, the gate driveis ensured. In addition, the gate drive unit includes two outputterminals, which can charge two gate lines simultaneously, and savingthe charging time.

The working stage is a period of time when the charging sub-unit isdischarging and outputting a gate high level after the pull-up sub-unit203 pulls up the voltage of the charging sub-unit.

The input voltage signal IN is an output signal of the gate drive unitof a previous stage, or a start voltage signal (STV).

Referring to FIG. 3, the charging sub-unit 201 includes a capacitor c.The buffer sub-unit 202 includes a first transistor T1, a sourceelectrode of the first transistor T1 is connected with the input voltagesignal IN, a gate electrode of the first transistor T1 is connected withthe source electrode of the first transistor T1, and a drain electrodeof the first transistor T1 is connected with a first terminal of thecapacitor C. The pull-up sub-unit 203 includes a second transistor T2and a third transistor T3. A source electrode of the second transistorT2 is connected with a clock signal CLK and a source electrode of thethird transistor T3, a gate electrode of the second transistor T2 and agate electrode of the third transistor T3 are both connected with thefirst terminal of the capacitor C, a drain electrode of the secondtransistor T2 is connected with a second terminal of the capacitor C andthe first output terminal OUTPUT(n), and a drain electrode of the thirdtransistor T3 is connected with the second output terminal OUTPUT(n+1).The holding sub-unit 204 includes a fourth transistor T4, a fifthtransistor T5, and a sixth transistor T6. A source electrode of thefourth transistor T4 is connected with a continuous high-level signalGCH, a gate electrode of the fourth transistor T4 is connected with thesource electrode of the fourth transistor T4, a drain electrode of thefourth transistor T4 is connected with a source electrode of the fifthtransistor T5 and a gate electrode of the sixth transistor T6, a gateelectrode of the fifth transistor T5 is connected with the firstterminal of the capacitor C, a drain electrode of the fifth transistorT5 is connected with a continuous low-level signal VGL, a sourceelectrode of the sixth transistor T6 is connected with the secondterminal of the capacitor C, and a drain electrode of the sixthtransistor T6 is connected with the continuous low-level signal VGL. Thedischarge sub-unit 205 includes a seventh transistor T7 and an eighthtransistor T8. A source electrode of the seventh transistor T7 isconnected with a reset signal RESET, a gate electrode of the seventhtransistor T7 is connected with the drain electrode of the fourthtransistor T4, a drain electrode of the seventh transistor T7 isconnected with a gate electrode of the eighth transistor T8, a sourceelectrode of the eighth transistor T8 is connected with the drainelectrode of the first transistor T1, and a drain electrode of theeighth transistor T8 is connected with a continuous low-level signalVSS.

FIG. 4 is a schematic diagram of signal timing provided by at least oneembodiment of the present disclosure, the operation process of the gatedrive unit provided by FIG. 3 will be described below with reference toFIG. 4.

A charging stage t1: when IN is at a high level, T1 is turned on, and apotential of the first terminal of capacitor C rises to charge thecapacitor C.

When the capacitor C is charged, the potential of the first terminal ofthe capacitor C reaches the threshold voltage of the transistor T5, T5is turned on, and a potential of PD node is pulled down under control ofthe low level VGL.

A working stage t2: when the high level of IN ends, CLK reaches a highlevel, and at this time, the potential of the first terminal of thecapacitor C is further pulled up under a bootstrap effect. The potentialof the first terminal of the capacitor C reaches the threshold voltageof transistors T2 and T3, T2 and T3 are turned on, and the two outputterminals output a high level of CLK as gate high level. In thisprocess, because the potential of the first terminal of the capacitor Cis further raised, after a voltage of the gate electrode of T5 is pulledup for a second time, a working current of T5 is raised, and thepotential of the PD node is pulled down for a second time.

In this stage, because the potential of PD node is at a low level, T6 isturned off, and VGL cannot be applied to the two output terminals,thereby avoiding the output terminals from being pulled down in advanceby VGL when the output terminals output the gate high level, andavoiding the abnormal signals.

A discharging stage t3: When the reset signal RESET is at a high level,T8 is turned on. Under control of a low level of VSS, the potential ofthe first terminal of the capacitor C is rapidly pulled down, and T2, T3and T5 are turned off. When T5 is turned off, PD node returns to a highpotential, T6 is turned on, VGL is applied to the output terminalOUTPUT(n), and output terminal OUTPUT(n) outputs a low level. When T2and T3 are turned off, the output terminal OUTPUT(n+1) is at a lowlevel.

A holding stage T4: PD node keeps the high potential under control ofGCH, T6 is turned on, VGL is continuously applied to the output terminalOUTPUT(n), and the output terminal OUTPUT(n) outputs a low level.Because T2 and T3 keep in a state of turn-off, the output terminalOUTPUT(n) also keeps a low level.

For example, the gate drive unit further includes a reset unit 206, andthe reset unit 206 is used for resetting the signal of the chargingsub-unit at end of one frame of scanning. As shown in FIG. 3, the resetunit 206 includes a ninth transistor T9, a source electrode of the ninthtransistor T9 is connected with the source electrode of the sixthtransistor T6, a drain electrode of the ninth transistor T9 is connectedwith the drain electrode of the sixth transistor T6, and a gateelectrode of the ninth transistor T9 is connected with a control signalGCL. The control signal GCL is at a high level at the end of one frameof scanning, and the control signal GCL controls T9 to be turned on,thereby writing VGL to the capacitor C. Of course, in this structure,VGL can be written without T9. Referring to FIG. 3, VGL can be writtenthrough T6, and setting T9 can ensure that signal reset can still beperformed in a case where T6 fails.

For example, T9 can also be used as a reserved test lighting switch. Byreplacing VGL and GCL signals with high-level signals, T6 is turned on,and the output terminal OUTPUT(n) outputs a high level, therebyimplementing a lighting test.

Optionally, the discharging sub-unit 205 can further include a tenthtransistor T0, a gate electrode of the tenth transistor T0 is connectedwith the drain electrode of the fourth transistor T4, a source electrodeof the tenth transistor T0 is connected with the source electrode of theeighth transistor T8, and a drain electrode of the tenth transistor T0is connected with the drain electrode of the eighth transistor T8. Inthe charging stage t1 and the working stage t2, the PD node is at a lowpotential, so that T0 is turned off, which does not affect the chargingof the capacitor C in the charging stage t1 and the outputting of theoutput terminal in the working stage t2. In the discharging stage t3,the PD node returns to a high potential, T0 is turned on, and thedischarging of the capacitor C is accelerated.

In the timing chart as shown in FIG. 4, RESET is a signal shift afterIN, so that RESET is also obtained according to the output signal of thegate drive unit of the previous stage or the start voltage signal (STV),which is convenient for circuit design. In other examples, RESET canalso be controlled by an independent signal.

For example, the first to tenth transistors may bemetal-oxide-semiconductor field-effect transistors (MOSFET).

In the embodiments of the present disclosure, the drive module furtherincludes a data drive unit, and the date drive unit is used forinputting data signals to the data lines in a column inversion mode.Sub-pixel units connected with a same data line are a column ofsub-pixel units. Using the column inversion mode can achieve a displayeffect similar to that of the dot inversion mode, the flicker problem ofa liquid crystal display panel adopting the dot inversion mode isminimized, and the column inversion mode is simpler than that of the dotinversion mode.

Polarity inversion refers to that when a same sub-pixel is displayed,the written voltages of one frame and the next frame are opposite inpolarity. In this way, the voltage of the next frame will be written toneutralize the original voltage of opposite polarity in the sub-pixelbefore writing the target voltage. According to the present disclosure,the scanning lines are turned on in advance by pre-charging, so thatvoltage neutralization and pre-writing are realized, and charging timeis shortened. Polar inversion includes frame inversion, columninversion, dot inversion, etc. Column inversion refers to thatpolarities of voltages of sub-pixels in adjacent columns are opposite,that is, polarities of voltages of adjacent sub-pixels in a same row areopposite, and polarities of voltages of adjacent sub-pixels in a samecolumn are same. Point inversion refers to that polarities of voltagesof any adjacent sub-pixels are opposite. Because the sub-pixels of asame column are arranged in a staggered arrangement in the presentdisclosure, in a case where the column inversion mode is used fordriving, not only the polarities of voltages of adjacent sub-pixels in asame row are opposite, but also the polarities of voltages of adjacentsub-pixels in a longitudinal direction are opposite, for example, inFIG. 1, the second sub-pixel in the first row and the first sub-pixel inthe second row implement a similar effect of the dot inversion.

The embodiments of the present disclosure further provide a displaypanel, and the display panel includes any of the above array substrates,such as the array substrate as shown in FIG. 1.

According to the embodiments of the present disclosure, two thin filmtransistors are arranged in each sub-pixel region to charge a pixelelectrode in corresponding sub-pixel region, and one gate line (exceptthe first one and the last one) is simultaneously connected with thinfilm transistors in two adjacent rows of sub-pixel regions. When acertain gate line is loaded with a voltage, thin film transistors in tworows of sub-pixel regions adjacent to the gate line are simultaneouslyturned on. At this time, a previous row of sub-pixel regions of the tworows of sub-pixel regions can be charged through a data line, and a nextrow of sub-pixel regions of the two rows of sub-pixel regions can bepre-charged at the same time. In this way, the time required forcharging the next row of sub-pixel regions becomes shorter, so that thisdesign can shorten the charging time of other rows of sub-pixel regionsexcept the first row and the last row of sub-pixel regions, and canrealize accurate writing of pixel voltages in a shorter time.

The embodiments of the disclosure further provide a display device,which includes the display panel. For example, the display deviceprovided by the embodiment of the present disclosure may be any productor component with a display function such as a mobile phone, a tabletcomputer, a television, a display, a notebook computer, a digital photoframe, a navigator, etc.

According to the embodiments of the present disclosure, two thin filmtransistors are arranged in each sub-pixel region to charge a pixelelectrode in corresponding sub-pixel region, and one gate line (exceptthe first one and the last one) is simultaneously connected with thinfilm transistors in two adjacent rows of sub-pixel regions. When acertain gate line is loaded with a voltage, thin film transistors in tworows of sub-pixel regions adjacent to the gate line are simultaneouslyturned on. At this time, a previous row of sub-pixel regions of the tworows of sub-pixel regions can be charged through a data line, and a nextrow of sub-pixel regions of the two rows of sub-pixel regions can bepre-charged at the same time. In this way, the time required forcharging the next row of sub-pixel regions becomes shorter, so that thisdesign can shorten the charging time of other rows of sub-pixel regionsexcept the first row and the last row of sub-pixel regions, and canrealize accurate writing of pixel voltages in a shorter time.

The above is only some example embodiments of the present disclosure andare not intended to limit the present disclosure. Any modification,equivalent substitution, improvement, etc. made within the principles ofthe present disclosure shall be included within the scope of protectionof the present disclosure.

What is claimed is:
 1. An array substrate, comprising a plurality ofgate lines and a plurality of data lines, wherein the plurality of gatelines and the plurality of data lines define rows of sub-pixel regions,each of the sub-pixel regions comprise two thin film transistors and apixel electrode, and the two thin film transistors are both connectedwith the pixel electrode; gate electrodes of two thin film transistorsin a sub-pixel region in an (n)th row of the rows of sub-pixel regionsare respectively connected with an (n)th gate line and an (n+1)th gateline of the plurality of gate lines, K≥n≥1, n and K are integers, and Kis an amount of rows of the sub-pixel regions; and a drive circuit;wherein the drive circuit comprises K+2 gate drive circuits arranged incascade, a first gate drive circuit of the K+2 gate drive circuits isconnected with a first gate line of the plurality of gate lines, a lastgate drive circuit of the K+2 gate drive circuits is connected with alast gate line of the plurality of gate lines, a (s)th gate drivecircuit of the K+2 gate drive circuits is simultaneously connected witha (s−1)th gate line and a (s)th gate line of the plurality of gatelines, and K+1≥s≥2.
 2. The array substrate according to claim 1, whereinthe two thin film transistors in the sub-pixel region in the (n)th roware respectively located on a first side and a second side of thesub-pixel region in the (n)th row, the first side and the second sideare oppositely disposed, and the first side and the second side aresides of the sub-pixel region where the two thin film transistors arelocated near the (n)th gate line and the (n+1)th gate line.
 3. The arraysubstrate according to claim 2, wherein thin film transistors connectedwith an (m)th gate line of the plurality of gate lines are symmetricallyarranged on both sides of the (m)th gate line, K≥m≥2, and m is aninteger.
 4. The array substrate according to claim 3, wherein the twothin film transistors each comprises an active layer, and a sourceelectrode and a drain electrode which are both arranged on the activelayer, and two thin film transistors symmetrically arranged on bothsides of a same gate line share one source electrode formed by sourceelectrodes of the two thin film transistors.
 5. The array substrateaccording to claim 4, wherein a part of a data line connected with eachof the two thin film transistors is reused as a source electrode of theeach of the two thin film transistors in the sub-pixel region in the(n)th row.
 6. A display panel, comprising the array substrate accordingto claim
 5. 7. The array substrate according to claim 1, wherein thinfilm transistors connected with an (m)th gate line of the plurality ofgate lines are symmetrically arranged on both sides of the (m)th gateline, K≥m≥2, and m is an integer.
 8. The array substrate according toclaim 1, wherein the two thin film transistors each comprises an activelayer, and a source electrode and a drain electrode which are botharranged on the active layer, and two thin film transistorssymmetrically arranged on both sides of a same gate line share onesource electrode formed by source electrodes of the two thin filmtransistors.
 9. The array substrate according to claim 1, wherein a partof a data line connected with each of the two thin film transistors isreused as a source electrode of the each of the two thin filmtransistors in the sub-pixel region in the (n)th row.
 10. The arraysubstrate according to claim 1, wherein an amount of sub-pixel regionsin each row of the rows of sub-pixel regions is equal, and sub-pixelregions in adjacent rows are staggered with respect to each other; andthin film transistors in an (a)th sub-pixel region of each row of therows of sub-pixel regions are both connected with a same data line,L≥a≥1, a and L are integers, and L is an amount of sub-pixel regions ineach row of the rows of sub-pixel regions.
 11. The array substrateaccording to claim 1, wherein the plurality of data lines each has arectangular wave shape.
 12. The array substrate according to claim 1,wherein the rows of sub-pixel regions comprises three types of sub-pixelregions that are of red, green and blue, respectively, any two adjacentsub-pixel regions are sub-pixel regions of different types, and the twoadjacent sub-pixel regions are two sub-pixel regions of a same row ordifferent rows.
 13. The array substrate of claim 1, wherein the drivecircuit further comprises A gate drive circuits, the A gate drivecircuits are not connected with any one of the plurality of gate lines,and A is a positive integer; and a (A+1)th gate drive circuit isconnected with the first gate line, (A+2)th to (K+1+A)th gate drivecircuits are respectively connected with two gate lines of the pluralityof gate lines, and a (K+2+A)th gate drive circuit is connected with thelast gate line.
 14. The array substrate according to claim 13, whereinthe gate drive circuit comprises: a charging sub-circuit; a buffersub-circuit, configured to receive an input voltage signal and chargethe charging sub-circuit by using the input voltage signal; a pull-upsub-circuit, comprising two output terminals, wherein the pull-upsub-circuit is configured to pull up a voltage of the chargingsub-circuit under control of a timing signal and output a gate highlevel through the two output terminals in a working stage; a holdingsub-circuit, configured to control the two output terminals of thepull-up sub-circuit to continuously output a low level during otherstages other than the working stage; and a discharging sub-circuit,configured to control the charging sub-circuit to discharge after end ofthe working stage.
 15. The array substrate according to claim 14,wherein the charging sub-circuit comprises a capacitor C; the buffersub-circuit comprises a first transistor T1, a source electrode of thefirst transistor T1 is connected with an input voltage signal IN, a gateelectrode of the first transistor T1 is connected with the sourceelectrode of the first transistor T1, and a drain electrode of the firsttransistor T1 is connected with a first terminal of the capacitor C; thepull-up sub-circuit comprises a second transistor T2 and a thirdtransistor T3, a source electrode of the second transistor T2 isconnected with a clock signal CLK and a source electrode of the thirdtransistor T3, a gate electrode of the second transistor T2 and a gateelectrode of the third transistor T3 are both connected with the firstterminal of the capacitor C, a drain electrode of the second transistorT2 is connected with a second terminal of the capacitor C and a firstoutput terminal, and a drain electrode of the third transistor T3 isconnected with a second output terminal; the holding sub-circuitcomprises a fourth transistor T4, a fifth transistor T5, and a sixthtransistor T6, a source electrode of the fourth transistor T4 isconnected with a continuous high-level signal GCH, a gate electrode ofthe fourth transistor T4 is connected with the source electrode of thefourth transistor T4, a drain electrode of the fourth transistor T4 isconnected with a source electrode of the fifth transistor T5 and a gateelectrode of the sixth transistor T6, a gate electrode of the fifthtransistor T5 is connected with the first terminal of the capacitor C, adrain electrode of the fifth transistor T5 is connected with acontinuous low-level signal VGL, a source electrode of the sixthtransistor T6 is connected with the second terminal of the capacitor C,and a drain electrode of the sixth transistor T6 is connected with thecontinuous low-level signal VGL; and the discharging sub-circuitcomprises a seventh transistor T7 and an eighth transistor T8, a sourceelectrode of the seventh transistor T7 is connected with a reset signal,a gate electrode of the seventh transistor T7 is connected with thedrain electrode of the fourth transistor T4, a drain electrode of theseventh transistor T7 is connected with a gate electrode of the eighthtransistor T8, a source electrode of the eighth transistor T8 isconnected with the drain electrode of the first transistor T1, and adrain electrode of the eighth transistor T8 is connected with acontinuous low-level signal VSS.
 16. The array substrate according toclaim 1, wherein the drive circuit further comprises a data drivecircuit, the data drive circuit is configured to input data signals tothe plurality of data lines in a column inversion mode, and sub-pixelcircuits connected with a same data line are a column of sub-pixelcircuits.
 17. A display panel, comprising an array substrate, whereinthe array substrate comprises: a plurality of gate lines and a pluralityof data lines, wherein the plurality of gate lines and the plurality ofdata lines define rows of sub-pixel regions, each of the sub-pixelregions comprise two thin film transistors and a pixel electrode, andthe two thin film transistors are both connected with the pixelelectrode; gate electrodes of two thin film transistors in a sub-pixelregion in an (n)th row of the rows of sub-pixel regions are respectivelyconnected with an (n)th gate line and an (n+1)th gate line of theplurality of gate lines, K≥n≥1, n and K are integers, and K is an amountof rows of the sub-pixel regions; and a drive circuit; wherein the drivecircuit comprises K+2 gate drive circuits arranged in cascade, a firstgate drive circuit of the K+2 gate drive circuits is connected with afirst gate line of the plurality of gate lines, a last gate drivecircuit of the K+2 gate drive circuits is connected with a last gateline of the plurality of gate lines, a (s)th gate drive circuit of theK+2 gate drive circuits is simultaneously connected with a (s−1)th gateline and a (s)th gate line of the plurality of gate lines, and K+1≥s≥2.18. A display device, comprising a display panel, wherein the displaypanel comprises: an array substrate, wherein the array substratecomprises: a plurality of gate lines and a plurality of data lines,wherein the plurality of gate lines and the plurality of data linesdefine rows of sub-pixel regions, each of the sub-pixel regions comprisetwo thin film transistors and a pixel electrode, and the two thin filmtransistors are both connected with the pixel electrode; gate electrodesof two thin film transistors in a sub-pixel region in an (n)th row ofthe rows of sub-pixel regions are respectively connected with an (n)thgate line and an (n+1)th gate line of the plurality of gate lines,K≥n≥1, n and K are integers, and K is an amount of rows of the sub-pixelregions; and a drive circuit; wherein the drive circuit comprises K+2gate drive circuits arranged in cascade, a first gate drive circuit ofthe K+2 gate drive circuits is connected with a first gate line of theplurality of gate lines, a last gate drive circuit of the K+2 gate drivecircuits is connected with a last gate line of the plurality of gatelines, a (s)th gate drive circuit of the K+2 gate drive circuits issimultaneously connected with a (s−1)th gate line and a (s)th gate lineof the plurality of gate lines, and K+1≥s≥2.